This position can be located in Portland, OR or in Santa Clara, CA
As part of the physical design team, own and implement large partitions of high-performance processor blocks using digital design implementation tools.
What the Team wants you to know
“I’ve never had so much exposure to our company strategy, roadmap and why we’re doing what we’re doing. The leadership has been open with everyone which makes you feel like you have a stake in the company’s success.”
What you’ll do
- Design and implement solutions using knowledge of timing, floor-planning, high speed design techniques, and formal verification techniques.
- Focus on EMIR flow set-up, systemic solutions across the design space and guide implementation engineers towards EMIR convergence
- Work with logic designers to optimize the design PPA (performance, power & area)
- Analyze the design micro architecture and apply to floorplan, synthesis and P&R of design.
- Apply semi-custom, and ASIC-methodologies, as required, to run, synthesis, placement, CTS, routing, and complete other physical design tasks to make the block ready for sign-off.
- Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
- Implement lower-geometry designs using CMOS-7nm rules, device characteristics to implement data-paths, and large physical blocks.
- Use state-of-the-art macro-compilers, design-cell libraries to provide appropriate design libraries to the processor design team.
What you’ll bring
- Minimum of 6 years of relevant experience in VLSI design, high-speed microprocessor design
- Staff level physical design engineer with focused expertise in EM/IR analysis and debug
- Preferable experience in EM/IR using Apache Redhawk/Seascape tool
- Experience in reliability verification, power integrity and package power distribution issues
- Hands on experience in high frequency power integrity analysis and challenges in deep submicron designs (preferably 7nm and 5nm nodes and lower nodes)
- Expertise in debugging PDN issues like Grid weakness, Dynamic/Static IR drop, SignalEM & ESD
- Automation using Python and Tcl
- Hands on experience in floor planning, place & route, power and clock distribution, pin placement and timing constraints generation
- Timing convergence using high speed design techniques
- Physical design of high frequency chips with emphasis on successful timing closure
- Excellent understanding of geometry/ process/ device technology implications on physical design. 16nm and 7nm experience is required
- Good understanding of static timing analysis (STA), EM/IR and sign-off flow
- Experience in physical design verification
- BS/MS in Electrical Engineering
Perks in Santa Clara
- Office has panoramic views of Silicon Valley
- Garage parking, including charging stations and bike parking
- Gym and café on campus
- Healthy snacks, espresso, and drinks
- Standing desks
- Game room, including ping-pong
- Unlimited Flextime and 10+ paid holidays
Perks in Portland
- Walking distance of breweries, landscaped parks, art galleries, restaurants and shops
- Garage parking
- On-site bike parking and repair station
- On-site café, bar and market
- Roof top terrace with Willamette River views
- Healthy snacks, espresso and drinks
- Standing/Ergo friendly desk set up
- Game room
- Unlimited Flextime and 10+ paid holidays
Ampere is designing the future of hyperscale cloud and edge computing with the world’s first cloud native processor. Built for the cloud with a modern 64-bit Arm server-based architecture, Ampere gives customers the freedom to accelerate the delivery of all cloud computing applications. With industry-leading cloud performance, power efficiency and scalability, Ampere processors are tailored for the continued growth of cloud and edge computing.
Like the scientist behind its name, Ampere employees are innovators. We understand the needs of cloud computing and different software requirements. We are inventing what comes next and looking at everything from the structure of memory and how efficient the system is, to considerations on speed, cost of electricity and ability to cool. Power, size, weight and cost are driving the technology requirements and the innovation to come.
Our world class team of engineers, with depth and expertise in the cloud and semiconductor industries, is not only focused on the development of new semiconductor designs but also building out the first software ecosystem for Arm®-based server processors. Through the Ampere approach to the cloud and edge, we give our customers the freedom to challenge the status quo and accelerate next-generation data centers for the most memory-intensive applications. Given the challenge we have outlined, we are building a culture of entrepreneurs that ensure customers come first, proactively approaching industry challenges in the areas of security, power and performance, delivering results that matter most.
We are an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability status, protected veteran status, or any other characteristic protected by law.