Design for Test (DFT) Design Engineer

  • Ampere
  • Santa Clara, CA, USA
  • Nov 08, 2021
Full time Engineering

Job Description

The Role

The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex 7nm server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. 

What you'll do

  • Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis
  • MBIST insertion, simulation and debug on RTL and gates netlist
  • Boundary Scan insertion, simulation and verification
  • Scan ATPG pattern generation, simulation and debug on RTL and gates netlist
  • Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys)
  • STA DFT Test mode timing constraint development and analysis
  • In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
  • ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data

What you'll bring

  • Minimum 12 years of industry experience
  • Minimum 8 years of relevant DFT experience
  • Expert with methods and techniques to design, implement and verify Memory BIST on repairable and non-repairable memories using Electrical fuses
  • Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions
  • Ability to code programmable and non-programmable MBIST controllers in Verilog
  • Solid understanding of MBIST algorithms needed for 7nm and lower technology nodes
  • Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level
  • Expert understanding of tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development
  • Hands on experience in usage of industry standard tools, like Mentor Tessent LV or Shell flow, or Synopsys SMS flow
  • Experience with pattern generation for test-equipment, and conversion using off-the-shelf tools like VTRAN
  • Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl
  • Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion

Education

  • BS or MS in Electrical Engineering or Computer Engineering

Perks in Santa Clara  

  • Office has panoramic views of Silicon Valley
  • Garage parking, including charging stations and bike parking
  • Gym and café on campus
  • Healthy snacks, espresso, and drinks 
  • Standing desks
  • Game room, including ping-pong 
  • Unlimited Flextime and 10+ paid holidays

Our Company  

Ampere is designing the future of hyperscale cloud and edge computing with the world’s first cloud native processor. Built for the cloud with a modern 64-bit Arm server-based architecture, Ampere gives customers the freedom to accelerate the delivery of all cloud computing applications. With industry-leading cloud performance, power efficiency and scalability, Ampere processors are tailored for the continued growth of cloud and edge computing.

Our Story  

Like the scientist behind its name, Ampere employees are innovators. We understand the needs of cloud computing and different software requirements. We are inventing what comes next and looking at everything from the structure of memory and how efficient the system is, to considerations on speed, cost of electricity and ability to cool. Power, size, weight and cost are driving the technology requirements and the innovation to come.

Our world class team of engineers, with depth and expertise in the cloud and semiconductor industries, is not only focused on the development of new semiconductor designs but also building out the first software ecosystem for Arm®-based server processors. Through the Ampere approach to the cloud and edge, we give our customers the freedom to challenge the status quo and accelerate next-generation data centers for the most memory-intensive applications.  Given the challenge we have outlined, we are building a culture of entrepreneurs that ensure customers come first, proactively approaching industry challenges in the areas of security, power and performance, delivering results that matter most.

We are an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability status, protected veteran status, or any other characteristic protected by law.